An arbiter circuit is a type of circuit which can determine which request to be replied to when two or more request signals compete with each other. As shown in FIG. 7, a conventional arbiter circuit 100 in a memory system can receive the write request signal and read request signal with respect to memory 102 in an asynchronous manner, and the arbiter circuit then determines the priority order for the two request signals. For example, the arbiter circuit may let the write command go first, followed by the read command.
FIG. 8 illustrates a configuration of a conventional arbiter circuit. Basically, the conventional arbiter circuit comprises the following parts: receiving circuit 104 which receives and holds a number, for example, two, request signals ARQ and BRQ; arbitration circuit 106 which conducts arbitration between the two request signals ARQ and BRQ when they compete with each other; and timing generating circuit 108 which generates at the prescribed timing command XIS (X=A or B) for executing the memory cycle corresponding to the request in the memory (not shown in the figure) corresponding to the request signal XRQ (X=A or B) selected by the arbitration circuit 106. These circuits are connected in series.
When a certain command XIS travels from timing generating circuit 108, it is fed back to receiving circuit 104, and a hold on request signal XRQ corresponding to said command XIS is released. Consequently, when request signal ARQ has priority out of the two competing request signals ARQ and BRQ, command AIS is output from timing generating circuit 108, and, either at the same time or a little later, request signal ARQ is released at receiving circuit 104; in the next cycle, the other request signal BRQ, which has been held in receiving circuit 104 up to that time, is selected by arbitration circuit 106, and command BIS is output from timing generating circuit 108.
However, with an increase in the integration density of the semiconductor memory in recent years, there are cases in which a number of memories are carried on a single chip. In this case, although on a single chip, the number of memories receive memory access independent from one another. Consequently, as shown in FIG. 8, for each memory, a conventional arbiter circuit is arranged. As a result, the memories operate independently (that is, asynchronously), and harmful noises are sent to each other.
For example, in a dynamic RAM, the small change (such as 100 mV) in the potential of the bit line, which has been precharged to a prescribed voltage, corresponding to the memory information of the memory cell is amplified by a sense amplifier and detected. When the other dynamic RAM works in an asynchronous manner during this delicate sensing operation, the noise generated there may affect the sensing voltage, and the read data may be ruined.
As shown in FIG. 9, in the conventional method, when each of a number (N) of memories receives a number of (for example, two) request signals (ARQ.sub.1, BRQ.sub.1), (ARQ.sub.2, BRQ.sub.2), . . . , (ARQ.sub.N, BRQ.sub.N) through the common receiving circuit 110, with competition taking place among these request signals ARQ.sub.1, BRQ.sub.1, ARQ.sub.2, BRQ.sub.2, . . . , ARQ.sub.N, BRQ.sub.N, arbitration is made by a common arbitration circuit 112. One of request signals XRQ.sub.i (X=A or B, i is any one of 1-N) is selected, and common timing generating circuit 114 generates, with a prescribed timing, command XIS.sub.i (X=A or B, i is any one of 1-N), which defines the memory cycle corresponding to request signal XRQ.sub.i selected with the priority, to the corresponding memory.
In this system, in which the arbitration processing is performed in a common arbiter circuit for the number of requests with respect to the number of memories, only one memory cycle can be generated at a time. Consequently, only one memory can operate at a time. As a result, the aforementioned problem related to mutual interference among the memories can be solved. However, when a number of request signals compete with each other for a number of memories, the request with the lowest priority has to wait until all of the requests with a priority level higher than it have been processed. Consequently, the mean memory access time of the overall system is prolonged, and the application efficiency of the memory is decreased. This is a disadvantage.
Also, for arbitration circuit 112, the design is made in consideration of the case of competition of any number among all of the request signals ARQ.sub.1 -BRQ.sub.N in any combination. Consequently, the number of circuit configurations corresponds to the number of memories, and it is difficult to achieve standardization.
Generally speaking, for the arbiter circuit shown in FIG. 9, while it is possible to handle a number of memories, as the number of memories is increased, the aforementioned disadvantage becomes more and more prominent. This is a disadvantage.
It is an object of the present invention to provide an arbiter circuit for a number of memories in which the memories can operate independently without mutual interference, and even when the number of memories is increased, the circuit configuration still does not become complicated, and the cost of the circuit still does not rise.